Enhancing SRAM Cell Circuitry through PDLPDC Optimization

  • Hemant Silawat TITM, Bhopal, M.P, India
  • Shivraj Singh TITM, Bhopal, M.P, India
Keywords: VLSI, SRAM, LPD, Delay Write, Delay Read, Low Power Dissipation, 6T, 10T, PDLPDC, Power Optimization


This study focuses on improving static random-access memory (SRAM) cell circuit design by leveraging the Power Dissipation Low Power Dissipation Circuit (PDLPDC). The PDLPDC, a low-power dissipation circuit, has gained widespread use in designing cells for read operations, write operations, and idle modes, contributing to power optimisation in submicron or nano-range Very Large Scale Integration (VLSI) designs. While various SRAM cells, including 6T and 10T configurations, have been developed, they often exhibit higher power consumption. In contrast, our PDLPDC-based approach operates at lower power levels. With the increasing integration of portable devices into everyday life, power optimisation has emerged as a critical challenge in modern VLSI technology. Many contemporary gadgets and systems rely on very Large-scale Integration (VLSI) technology, where static random-access memory (SRAM) blocks occupy substantial chip space and represent a significant source of leakage power in current systems. However, a common practice, scaling the supply voltage of SRAM macros can lead to elevated power dissipation. This research addresses the challenge by efficiently scaling the supply voltage of SRAM macros, resulting in an overall reduction in power dissipation. The study introduces 6T and 10T SRAM circuits that minimise power dissipation during read and write operations while maintaining reasonable performance and stability. The impact of process parameter variations on various design metrics, including read and write power, leakage power, leakage current, and latency, becomes a critical consideration in SRAM cell design with increased integration scale. The proposed circuit, optimised for the minimum power-delay product during read, write, and idle modes, is compared with traditional SRAM cells (6T and 10T) and demonstrates superior performance, reliability, and power efficiency. This research contributes to advancing the understanding of SRAM circuit design, especially in the context of power optimisation and process variations.


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How to Cite
Silawat, H., & Singh, S. (2023). Enhancing SRAM Cell Circuitry through PDLPDC Optimization. International Journal of Advanced Computer Technology, 12(6), 16-21. Retrieved from https://ijact.org/index.php/ijact/article/view/140