A Survey on Layout Implementation and Analysis of Different SRAM Cell Topologies

Sushmita Jain; Naveen khare

Sushmita Jain Babulal Tarabai Institute of Research & Technology, Sagar (MP), India
Naveen khare Babulal Tarabai Institute of Research & Technology, Sagar (MP), India

Keywords: Very Large-Scale Integrated Circuits, Device Circuit, SRAM, Delay Write, Delay Read, power delay product optimization, Low Power Design, Energy Efficient Device

Abstract

Because powered widgets are frequently used, the primary goal of electronics is to design low-power devices. Because of its applications in low-energy computing, memory cell operation with low voltage consumption has become a major interest in memory cell design. Because of specification changes in scaled methodologies, the only critical method for the success of low-voltage SRAM design is the stable operation of SRAM. The traditional SRAM cell enables high-density and fast differential sensing but suffers from semi-selective and read-risk issues. The simulation results show that the proposed design provides the fastest read operation and overall power delay product optimization. Compared to the current topologies of 6T, 8T, and 10T, while a traditional SRAM cell solves the reading disruption problem, previous strategies for solving these problems have been ineffective due to low efficiency, data-dependent leakage, and high energy per connection. Our primary goal is to reduce power consumption, improve read performance, and reduce the area and power of the proposed design cell work. The proposed leakage reduction design circuit has been implemented on the micro-wind tool. Delay and power consumption are important factors in memory cell performance. The primary goal of this project is to create a low-power SRAM cell.

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