International Journal of Advanced Computer Technology

An Improved Reversible Data Hiding with Hierarchical Embedding for Encrypted Images and BBET

2024-01-11T09:34:24+00:00

This research introduces an enhanced reversible data hiding (RDH) approach incorporating hierarchical embedding for encrypted images and employs a novel technique termed BBET (Best Bits Embedding Technique). RDH involves concealing information within a host sequence, enabling the restoration of both the host sequence and embedded data without loss from the marked sequence. While RDH has traditionally found applications in media annotation and integrity authentication, its utilisation has expanded into diverse fields. Given the rapid advancements in digital communication, computer technologies, and the Internet, ensuring information security poses a formidable challenge in safeguarding valuable data. Various reversible and stenographic techniques exist for covertly embedding or protecting data, spanning text, images, and protocols, and facilitating secure transmission to intended recipients. An influential approach in data security is reversible data hiding in encrypted images (RDHEI). This paper distinguishes between the conventional RDHEI technique, characterised by lower Peak Signal-to-Noise Ratio (PSNR) and higher Mean Squared Error (MSE), and proposes an improved RDHEI technique. As the prevalence of digital techniques for image transmission and storage rises, preserving image confidentiality, integrity, and authenticity becomes paramount. Text associated with an image, such as authentication or author information, can serve as embedded data. The recipient must adeptly recover both the concealed data and the original image. Reversible data-hiding techniques ensure the exact recovery of the original carrier after extracting the encrypted data. Classification of RDHEI techniques is based on the implemented method employed. This paper delves into a comprehensive exploration of techniques applicable to difference expansion, histogram shifting, and compression embedding for reversible data hiding. Emphasis is placed on the necessity for a reversible data-hiding technique that meticulously restores the host image.

Furthermore, the study evaluates performance parameters associated with encryption processes, scrutinising their security aspects. The investigation utilises the MATLAB tool to develop the proposed BBET technique, comparing its efficacy in embedding and achieving enhanced security features. The BBET technique is characterised by reliability, high robustness, and secure data hiding, making it a valuable addition to the evolving landscape of reversible data hiding methodologies.

Image Enhancement Based on Histogram Equalization with Linear Perception Neural Network Method

2023-12-04T13:14:19+00:00

Image enhancement poses a formidable challenge in low-level image processing. While various strategies, such as histogram equalisation, multipoint histogram equalisations, and picture element-dependent contrast preservation, have been employed, the efficacy of these approaches has not consistently met expectations. In response, this paper proposes a novel image enhancement method based on a linear perception neural network, demonstrating superior results in contrast improvement with brightness preservation. The proposed method leverages the interdependence of image components through a linear perceptron network, incorporating curvelet transform for image transformation into a multi-resolution mode. This transformative approach identifies component differences in picture elements, establishing a dependency characteristic matrix as a weight vector for the perceptron network. The perceptron network dynamically adjusts the weights of input image values, enhancing contrast while preserving brightness. Extensive testing of the image interdependence linear perception neural network method for contrast improvement has been conducted on multiple images. To quantify brightness preservation, comparative analysis with existing image enhancement strategies, such as histogram equalisation, was performed using Absolute Mean Brightness Error (AMBE) metrics. A smaller AMBE value indicates better preservation, while the Peak signal-to-noise ratio (PSNR) was employed to measure contrast improvement, with higher PSNR values indicating superior results. The proposed method (LPNNM) was rigorously evaluated against the conventional histogram equalisation (HE) technique for image enhancement. The results demonstrated that the LPNNM method outperforms HE in terms of both brightness preservation (as indicated by AMBE) and contrast improvement (as indicated by PSNR). This research contributes a robust and effective solution to the challenge of image enhancement, offering a more advanced alternative to existing methodologies.

Enhancing SRAM Cell Circuitry through PDLPDC Optimization

2023-12-04T13:30:53+00:00

This study focuses on improving static random-access memory (SRAM) cell circuit design by leveraging the Power Dissipation Low Power Dissipation Circuit (PDLPDC). The PDLPDC, a low-power dissipation circuit, has gained widespread use in designing cells for read operations, write operations, and idle modes, contributing to power optimisation in submicron or nano-range Very Large Scale Integration (VLSI) designs. While various SRAM cells, including 6T and 10T configurations, have been developed, they often exhibit higher power consumption. In contrast, our PDLPDC-based approach operates at lower power levels. With the increasing integration of portable devices into everyday life, power optimisation has emerged as a critical challenge in modern VLSI technology. Many contemporary gadgets and systems rely on very Large-scale Integration (VLSI) technology, where static random-access memory (SRAM) blocks occupy substantial chip space and represent a significant source of leakage power in current systems. However, a common practice, scaling the supply voltage of SRAM macros can lead to elevated power dissipation. This research addresses the challenge by efficiently scaling the supply voltage of SRAM macros, resulting in an overall reduction in power dissipation. The study introduces 6T and 10T SRAM circuits that minimise power dissipation during read and write operations while maintaining reasonable performance and stability. The impact of process parameter variations on various design metrics, including read and write power, leakage power, leakage current, and latency, becomes a critical consideration in SRAM cell design with increased integration scale. The proposed circuit, optimised for the minimum power-delay product during read, write, and idle modes, is compared with traditional SRAM cells (6T and 10T) and demonstrates superior performance, reliability, and power efficiency. This research contributes to advancing the understanding of SRAM circuit design, especially in the context of power optimisation and process variations.