# Design of Low Power and Power Scalable Pipelined ADC Using Current Modulated Power Scale

Keywords:
Pipelined ADC, CMOS, low power, memory effect, opamp sharing, subsampling

### Abstract

*This work represents a power scalable pipelined ADC, which **achieves** low power variation depends upon the sampling rate and enables variation in throughput. The keys to power scalability at high sampling rates were current modulation-based architecture and the development of novel rapid power-on Op-amp, which can completely and quickly power on/off by the feedback approach. The result achieved in this design is as high as 50 Msps and as low as 1 ksps, keeping some important parameters of ADC as ENOB and SNDR are almost constant. Power variation in ADC has a flexible range from 7.5 µW to 17 mW, which is lower power consumption than previous works.*

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### References

1. Arias, J., Boccuzzi, V., Quintanilla, L., Enrı´quez, L., Bisbal, D., Banu, M., “Low-power pipeline ADC for Wireless LANs," IEEE Journal of Solid-State Circuits, 39(8), pp.1338–1340, 2004.

2. Limotyrakis, S., Kulchycki, S. D., Su, D. K., & Wooley, B. A., “A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC”, IEEE Journal of Solid-State Circuits, 40(5), pp.1057–1067, 2005.

3. Miyazaki, D., Kawahito, S., & Furuta, M., “A 10-b 30- MS/s low-power pipelined CMOS AD converter using a pseudo-differential architecture”, IEEE Journal of Solid-State Circuits, 38(2), pp. 369–373, 2003.

4. Lee, S. C., Kim, K. D., Kwon, J. K., Kim, J., & Lee, S. H., “A 10-bit 400-MS/s 160-mW 0.13-mm CMOS dual-channel pipeline ADC without channel mismatch calibration”, IEEE Journal of Solid-State Circuits, 41(7), pp.1596–1605, 2006.

5. Hsueh, K.-W., Chou, Y.-K., & Tu, Y.-H, “A 1 V 11b 200MS/s pipelined ADC with digital background calibration in 65 nm CMOS”, ISSCC Digital Technical Papers, 30(4), pp.546–547, 2008.

6. Iroaga, E., & Murmann, B., “A 12-bit 75-MS/s pipelined ADC using incomplete settling. IEEE Journal of Solid-State Circuits”, 42(4), pp.748–756, 2007.

7. Enz, “CMOS Low-power analog circuit design, Designing Low Power Digital Systems," Emerging Technologies," pp. 79-133, 1996

8. Lewis, S. H., Scott Fetterman, H., Gross, G. F., Ramachandran, Jr. R., & Viswanathan, T. R., “A 10-b 20-M sample/s analog-to-digital converter”, IEEE Journal of Solid-State Circuits, 27(3), 351–358, 1992.

9. Jin-Fu Lin; Soon-Jyh Chang; Chun-Cheng Liu; Chih-Hao Huang, "A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, no.3, pp.163-167, March 2010

10. Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo, "A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications", IEEE Journal of Solid-State Circuits, vol.43, no.2, pp.321-329, Feb. 2008

11. Ryu, S.T.; Song, B.S.; Bacrania, K., "A 10-bit 50-MS/s Pipelined ADC With Op-amp Current Reuse", IEEE Journal of Solid-State Circuits, vol.42, no.3, pp.475-485, March 2007

12. Masato Yoshioka et al, “10-bit, 125 Ms/s, 40 mW Pipelined ADC in 0.18 µm CMOS”,FUJISU Sci.J,42,2,248-257(April 2006)

13. Jipeng Li; Un-Ku Moon, "A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique,", IEEE Journal of Solid-State Circuits, vol.39, no.9, pp. 1468- 1476, Sept. 2004

14. D. Miyazaki et al., "A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudo-differential architecture", IEEE Journal of Solid-State Circuits, vol 38, February 2003, pp. 369-373

15. D. Chang et al., "A 1.4-V 10-bit 25 MS/s pipelined ADC using Op-amp-reset switching technique", IEEE Journal of Solid-State Circuits, vol 38, August 2003, pp. 1401-1404

16. B. Hernes et al, “A 1.2V 220MS/s 10b Pipeline ADC Implemented in 0.13μm Digital CMOS”,IEEE International Solid-State Circuits Conference (ISSCC), vol 47, February 2004, pp. 256-257

17. K. Gulati et al., "A Low-Power Reconfigurable Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, vol 36, December 2001, pp. 1900-1911.

2. Limotyrakis, S., Kulchycki, S. D., Su, D. K., & Wooley, B. A., “A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC”, IEEE Journal of Solid-State Circuits, 40(5), pp.1057–1067, 2005.

3. Miyazaki, D., Kawahito, S., & Furuta, M., “A 10-b 30- MS/s low-power pipelined CMOS AD converter using a pseudo-differential architecture”, IEEE Journal of Solid-State Circuits, 38(2), pp. 369–373, 2003.

4. Lee, S. C., Kim, K. D., Kwon, J. K., Kim, J., & Lee, S. H., “A 10-bit 400-MS/s 160-mW 0.13-mm CMOS dual-channel pipeline ADC without channel mismatch calibration”, IEEE Journal of Solid-State Circuits, 41(7), pp.1596–1605, 2006.

5. Hsueh, K.-W., Chou, Y.-K., & Tu, Y.-H, “A 1 V 11b 200MS/s pipelined ADC with digital background calibration in 65 nm CMOS”, ISSCC Digital Technical Papers, 30(4), pp.546–547, 2008.

6. Iroaga, E., & Murmann, B., “A 12-bit 75-MS/s pipelined ADC using incomplete settling. IEEE Journal of Solid-State Circuits”, 42(4), pp.748–756, 2007.

7. Enz, “CMOS Low-power analog circuit design, Designing Low Power Digital Systems," Emerging Technologies," pp. 79-133, 1996

8. Lewis, S. H., Scott Fetterman, H., Gross, G. F., Ramachandran, Jr. R., & Viswanathan, T. R., “A 10-b 20-M sample/s analog-to-digital converter”, IEEE Journal of Solid-State Circuits, 27(3), 351–358, 1992.

9. Jin-Fu Lin; Soon-Jyh Chang; Chun-Cheng Liu; Chih-Hao Huang, "A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, no.3, pp.163-167, March 2010

10. Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo, "A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications", IEEE Journal of Solid-State Circuits, vol.43, no.2, pp.321-329, Feb. 2008

11. Ryu, S.T.; Song, B.S.; Bacrania, K., "A 10-bit 50-MS/s Pipelined ADC With Op-amp Current Reuse", IEEE Journal of Solid-State Circuits, vol.42, no.3, pp.475-485, March 2007

12. Masato Yoshioka et al, “10-bit, 125 Ms/s, 40 mW Pipelined ADC in 0.18 µm CMOS”,FUJISU Sci.J,42,2,248-257(April 2006)

13. Jipeng Li; Un-Ku Moon, "A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique,", IEEE Journal of Solid-State Circuits, vol.39, no.9, pp. 1468- 1476, Sept. 2004

14. D. Miyazaki et al., "A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudo-differential architecture", IEEE Journal of Solid-State Circuits, vol 38, February 2003, pp. 369-373

15. D. Chang et al., "A 1.4-V 10-bit 25 MS/s pipelined ADC using Op-amp-reset switching technique", IEEE Journal of Solid-State Circuits, vol 38, August 2003, pp. 1401-1404

16. B. Hernes et al, “A 1.2V 220MS/s 10b Pipeline ADC Implemented in 0.13μm Digital CMOS”,IEEE International Solid-State Circuits Conference (ISSCC), vol 47, February 2004, pp. 256-257

17. K. Gulati et al., "A Low-Power Reconfigurable Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, vol 36, December 2001, pp. 1900-1911.

Published

2020-10-25

How to Cite

*International Journal of Advanced Computer Technology*,

*9*(5), 16-20. Retrieved from http://ijact.org/index.php/ijact/article/view/63

Section

Articles